VLSI Test Principles and Architectures: Design for Testability
The Morgan Kaufmann Series in Systems on Silicon
Series editor Wayne Wolf
1st. edition, Morgan Kaufmann Publishers, Elsevier, 2006
(ISBN: 978-0-12-370597-6)
Chapter 2: Design for Testability, pp 37 - 96
Chapter 3: Logic and Fault Simulation, pp 105 - 154
in Chapter 4: Test Generation; Sections 4.1-4.6 and 4.10-4.12, pp 161 - 207, 231 - 248
Chapter 5: Logic Built-In Self-Test, pp 263 - 327
Chapter 6: Test Compression, pp 341 - 389
Chapter 8: Memory Testing and Built-In Self-Test, pp 461 - 509
Chapter 10: Boundary Scan and Core-Based Testing, pp 557 - 612
in Chapter 12: Test Technology Trends in the Nanometer Age; Section 12.2-12.4, pp 685 - 711
Integrated Circuit Test Engineering - Modern Techniques
Springer-Verlag London Ltd., 2006
VLSI Testing: digital and mixed analogue/digital techniques
IEE Circuits, Devices and Systems Series, Vol. 9
Series editors D.G. Haigh, R.S. Soin and J. Wood
The Institution of Electrical Engineers, 1998 (ISBN 0-85296-901-5)
Chapter 6: Test of structured digital circuits and microprocessors, pp 297 - 371
Chapter 9: The economics of test and final overall summary, pp 477 - 509
Campusnet10-3 *
Campusnet12-1 *
Lecture Notes on Test of Digital Logic
ID, DTU, January 1992
Chapter 3: Test Pattern Generation, pp 3.9 - 3.19
Campusnet03-2 *
Digital Systems Testing and Testable Design
W.H. Freeman, Computer Science Press, 1990
Section 9.9: Some Advanced Scan Concepts, pp 385 - 395
Campusnet06-3
`Problems on Test of Digital Logic' and `Solutions to Problems on ...'
1.1, 2.1-2.2, 3.1-3.4, 4.1-4.4, 5.1-5.3, 6.1-6.4, 7.1-7.2, 8.1-8.2, 9.1-9.4, 10.1, 11.1-11.4, 12.1-12.2
Assignment 2: Transition Faults Testing Using 1149.1 Boundary Scan
Assignment 3: Approximate Scan Logic
Digital Test Methods - IDDQ Tutorial
Test Technologists Team, Inc, 1996, pp 13.1-13.29
Automatic Test Pattern Generation
in The VLSI Handbook, Second Edition CRC Press 2006, Chapter 69, pp 69.1 69.18
Testing Embedded Toggle Generation Through On-Chip IR-Drop Measurements,
IEEE Design & Test of Computers, Vol.39/5, October 2022, pp 79-87
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set
in Proceedings of IEEE VLSI Test Symposium, May 2000, pp 15-20
Bridging Fault Modeling and Simulation for Deep Submicron CMOS ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
August 2002, T-CAD-21/8, pp 941-953
Efficient Sequential Test Generation Based on Logic Simulation
IEEE D&T of Computers, Vol. 19/5, pp 56-64, September 2002
Survey of low-power testing of VLSI circuits,
IEEE Design & Test of Computers, Vol.19/3, May 2002, pp 82-92
An Optimized Test During Burn-In for Automotive SoC
IEEE Design & Test, Vol. 35/3, pp 46-53, June 2018
Achieving at-speed structural test,
IEEE Design & Test of Computers, Vol.20/5, October 2003, pp 26-33
High-frequency, at-speed scan testing,
IEEE Design & Test of Computers, Vol.20/5, October 2003, pp 17-25
Scan Integrity Tests for EDT Compression
IEEE Design & Test, Vol. 37/4, pp 21-26, July/August 2020
Usable Circuits with Imperfect Scan Logic
Proceedings 2022 IEEE 31st Asian Test Symposium (ATS), pp 156-161, November 2022
Test Sequences for Faults in the Scan Logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
Vol. IEEE-TVLSI-30/10, pp. 1568-1572, October 2022
Using March Tests to Test SRAMs
IEEE Design & Test of Computers, Vol. 10/1, March 1993, pp 8-14
An Industrial Evaluation of DRAM Tests
IEEE Design & Test of Computers, Vol. 21/5, September 2004, 430-440
An Industrial Study of System-Level Test
IEEE Design & Test of Computers, Volume 29/1, January/February 2012, pp 19-27
Designing Next Generation Test Systems - An In-Depth Developers Guide
National Instruments Corporation, 2007, Chapter 1
Expedited-Compact Architecture for Average Scan Power Reduction
IEEE Design & Test of Computers, Vol. 30/3, pp 25-33, May/June 2013
IEEE Std. P1687.1 for Access Control of Reconfigurable Scan Networks
in Proceedings 2020 IEEE European Test Symposium (ETS), May 2020, 2 pages
Test Sequence-Optimized BIST for Automotive Applications
in Proceedings 2020 IEEE European Test Symposium (ETS), May 2020, 6 pages
Applying IEEE Test Standards to Multidie Designs
IEEE Design & Test of Computers, Vol. 39/5, pp 7-16, September/October 2022
Novel Technique for Manufacturing, System-Level, and In-System Testing
of Large SoC Using Functional Protocol-Based High-Speed I/O
IEEE Design & Test of Computers, Vol. 40/4, pp 17-24, July/August 2023
An Inside Job: Remote Power Analysis Attacks on FPGAs
IEEE Design & Test of Computers, Vol. 38/3, pp 58-66, May/June 2021
Recycling Test Methods to Improve Test Capacity and Increase Chip Shipments
IEEE Design & Test of Computers, Vol. 40/3, pp 45-52, May/June 2023
True Interactive Testing Based on IJTAG
IEEE Design & Test of Computers, Vol. 41/6, pp 62-69, November 2024
Low Power Design for Testability
in System-on-Chip Test Architectures: Nanometer Design for Testability
eInfochips Ltd., 2017
Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey
in CAD for Gigascale SoC Design and Verification Solutions
Hindawi Publishing Co., VLSI Design, Volume 2011, Article ID 948926, 7 pages
A BIST TPG for low power dissipation and high fault coverage,
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
IEEE-TVLSI-15/7, pp. 777-789, June 2007
Scan chain configuration based X filling for lowpower and high quality testing
IET Journal on Computers and Digital Techniques, vol. 4, pp. 1-13, 2010
LOC, LOS and LOES LOC, LOS and LOES at-speed testing methodologies
for automatic test pattern generation using transition delay fault model,
International Journal of Research in Engineering and Technology, IJRET-3/3, pp. 273-277, March 2014
Launch-on-Shift-Capture Transition Tests,
Proceedings IEEE International Test Conference, 2008, Paper 35.3, pp 1-9
At-speed Test on the QorIQTM P2020 Platform,
Proceedings IEEE International Test Conference, 2009, Lecture 3.3, pp 1-8
Conventional Tests for Approximate Scan Logic
IEEE Design & Test, Vol. 41/3, pp 5-13, May/June 2024
Approximate computing: A survey
IEEE Design & Test of Computers, Vol. 33/1, pp. 8-22, February 2016
Online scan diagnosis: A novel approach to volume diagnosis
Proceedings International Test Conference, October 2018, pp 1-10
Test generation for designs with multiple clocks
Proceedings Design Automation Conference, pp. 662-667, June 2003