assignment

Assignment: Low-Power Testing for IP Core-Based SoC

Low-power design is a major objective for high-performance, portable computing devices. Also, low power dissipation is becoming critical during manufacturing test, affecting test throughput and yield, as the system may consume significantly more power during test than during normal mode of operation. A modular design approach, using IP cores in SoC, has exaggerated the test power issue.

Several low-power testing techniques have been proposed to solve the low-power testing issues. Broadly, these test techniques apply to low-power scan testing or apply during built-in self-test (BIST). Low-power testing techniques of embedded IP cores is discussed in this problem.

Based on the literature below, the following issues must be discussed:

Discuss problems and concerns arising from excessive power consumption during test application and present the basic terminologies of power modeling
Present different power reduction techniques for scan-based design, reducing switching activity during test application
Present different power reduction techniques for low-power built-in self test, reducing switching activity during test application
Discuss the suitability of the low-power built-in self test techniques for IP core-based designs

Suggestions for literature

P. Girard, X. Wen, and Nur A. Touba,
`Low Power Testing',
in `System-on-Chip Test Architectures: Nanometer Design for Testability',
Morgan Kaufmann ed., 2007, Chapter 7, pp. 7.0-7.46
M.M. Patel and N. Nanavati ,
`Low Power Design for Testability',
in `System-on-Chip Test Architectures: Nanometer Design for Testability',
eInfochips Ltd., 2017
U. Mehta, K. Dasgupta, and N. Devashrayee,
`Suitability of Various Low-Power Testing Techniques for IP Core-Based SoC: A Survey',
in `CAD for Gigascale SoC Design and Verification Solutions',
Hindawi Publishing Co., VLSI Design, Volume 2011, Article ID 948926, 7 pages
S. Wang ,
`A BIST TPG for low power dissipation and high fault coverage',
IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
IEEE-TVLSI-15/7, pp. 777-789, June 2007
Z. Chen, J. Feng, D. Xiang, and B. Yin,
`Scan chain configuration based X filling for lowpower and high quality testing',
The Institution of Engineering and Technology,
IET Journal on Computers and Digital Techniques, vol. 4, pp. 1-13, 2010