Assignment: Transition Faults Testing using 1149.1 Boundary Scan

Transition delay faults (TDFs) model defects that delay rising or falling transitions on signals propagating through the circuit. Typical examples of TDFs are faults caused by rise and fall time variations.
While the stuck-at fault model considers a node stuck at a value (0/1), the transition fault model considers a node, whose value change although not within the specified time.

In at-speed testing, the functionality and integrity of an IC is tested while the system runs at operating speed. At-speed testing allows targeting defects due to timing-related issues. In this problem, the implementation of at-speed testing using the IEEE 1149.1 Boundary Scan is discussed.
Several at-speed scan testing techniques have been discussed:
Launch-on-shift (LOS):
The transition of a logic value is launched by the last clock pulse of the scan shift operation, and the transition is captured by the consecutive system clock pulse in capture mode.
Using muxed scan enable to define shift/capture modes implies a transition within a short period of the clock cycle, i.e. presenting an at-speed timing constraint on the scan enable signal.
Launch-off-capture (LOC): (a.k.a double-capture or broad-side test)
The transition is launched in the capture period, and the transition is derived from combinational logic or primary inputs.
The timing constraint on the scan enable signal is relaxed, most likely, at the cost of transition fault coverage.
Launch-on-shift-capture (LOSC), launch-on-capture-shift (LOCS):
A three-pattern test for transition faults that launches transitions combining LOS and LOC mechanisms.

Based on the literature below, the following issues must be discussed:

Suggestions for literature