Assignment: Approximate Scan Logic

The "approximate scan logic" method as introduced by Irith Pomeranz in the IEEE Design & Test Magazine May 2024 is considered.
Traditional scan-based testing is designed to identify faults that make chips unusable. Approximate scan logic refers to scan logic with faults that can be tolerated and is used for the application of scan-based tests targeting faults in the functional logic. The tests for the functional logic are adjusted to accommodate the presence of faults in the scan logic.

Pomeranz's approach acknowledges that certain defects, such as minor timing issues or localized failures, may be acceptable in applications where perfect operation is not mandatory, allowing for continued use of a chip rather than discarding it for minor imperfections. In the context of approximate scan logic, tolerable faults are those that do not critically affect the overall functionality of the chip despite being detected in the scan chain. These faults are often not catastrophic and might only marginally reduce performance or accuracy.

Based on the literature below, the following issues must be discussed:

• Discuss the "approximate scan logic" method, its use and potential.
• Explain the use of functional tests and conditions for approximate scan logic
• Explain the requirement of scan chain diagnosis
• Outline the test generation procedure