We reserve the right to change the examination syllabus below until the latest time required by DTU rules and regulations.
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Neil H.E. Weste and David M. Harris CMOS VLSI Design Addison-Wesley, 4th. edition, 2011 |
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Chapter 1: Introduction
1.1 - 1.5, 1.6, 1.8, 1.10
Chapter 2: MOS transistor theory
2.1 - 2.6
Chapter 3: CMOS processing technology
3.1 - 3.8
Chapter 4: Delay
4.1 - 4.8
Chapter 5: Power
5.1 - 5.7
Chapter 6: Interconnect
6.1 - 6.6
Chapter 7: Robustness
7.1 - 7.4 Chapter 9: Combinational Circuit Design 9.1 - 9.3 Chapter 10: Sequential Circuit Design 10.1 - 10.4 (including 10.3.11) Chapter 12: Array Subsystems 12.1-12.4, 12.6 Chapter 13: Special-Purpose Subsystems 13.1-13.4 Chapter 14: Design Methodology and Tools 14.1, 14.3-14.5 |
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Additional required readings (available on DTU Learn) |
1) Lecture Note Design for low-power,
Alberto Nannarelli, DTU. 2) Design Rules and Electrical Parameters for a 90 nm CMOS Process , Flemming Stassen, DTU. |
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Other required readings (available on DTU Learn) |
1) Course lecture slides 2) Knowledge of Problems and Solutions used during the course 3) Knowledge of the Lab Exercises used during the course 4) Knowledge of Chapter 9 Synthesis, in Douglas Perry, VHDL Programming by Example (4th Ed., McGraw-Hill 2002) 5) Examples of previous exam sets: E02205_F22, E02205_F23, E02205_F24, E02205_S24, E02205_F15_P2, E02205_F16_P1 |