DTU 02211: Research Topics in Computer Architecture - Async Ed. 2026

About the course

The course will approach some of the biggest modern architecture design problems from an unusual low level perspective: Asynchronous Circuit and System Design.
In the first third we will start off with the basics in asynchronous design and then follow up with selected major architecture challenges and how to think about them differently in the second third.
The first 10 weeks we will have lectures and labs and the final weeks you will work as a group on a selected project on computer architecture and integrated circuits.
The course is directly inspired by the two courses "02204: Introduction to Asynchronous Circuit Design" by Jens Sparsø (DTU) and "EENG426: Silicon Compilation" by Rajit Manohar (Yale University)

Preparation Lab (Lab 0):

You will have a preparation lab in which you prepare your computer for the labs 1-3. There is no hand in.

Labs 1 - 3:

You will work on practically applying the knowledge you learned about in the lectures. you will work in assigned groups and you will need to submit a short report and your results. You will need to pass all labs.

Project (Lab 4):

As a self formed group you will be given a project. Further you will prepare a final report on that project. Only your performance on the presentation/oral exam and report will be graded. More details will follow.

Group composition:

For Lab 0 to 3 you will be assigned to changing groups. For the final lab - the presentation you can form your group yourself.

Reference Book:

A book to step deeper into the topics for the first third is "Introduction to Asynchronus Circuit Design" by Jens Sparsø
ASYNC Introduction to Asynchronus Circuit Design

Jens Sparsø

Download this Book

  • from dtu orbit PDF.

Learning Platform:

All instructions, preparation or reading tasks will be published in form of a checklist around one week before the class.

The living lecture schedule (check DTU learn for updates):

  1. Intro, Asynchronus Fundamentals
  2. Dataflow design and dataflow to circuits
  3. Communicating Hardware Processes (CHP)
  4. From CHP to Production rules
  5. Bubble reshuffling, reset and sizing
  6. (clock) domain crossing, meta stability and non-determinism
  7. Performance scaling, gating and Memory Design
  8. Compute in Memory
  9. Networks on chip (Guest)
  10. TBD (Guest)
  11. Systolic Arrays (AI/TPU)
  12. TBD (Guest)
  13. Presentation preparation

The living lab schedule:

  1. Lab 0: get you PC ready and install the tools
  2. Lab 0: get you PC ready and install the tools
  3. Lab 1: Production rule and CHP simulation
  4. Lab 1: Production rule and CHP simulation
  5. Lab 2: Dataflow circuits
  6. Lab 2: Dataflow circuits
  7. Lab 3: Standard cells
  8. Lab 3: Standard cells
  9. Lab 4: Project work
  10. Lab 4: Project work
  11. Lab 4: Project work
  12. Lab 4: Project work
  13. Lab 4: Project work